In certain applications, such as analog to digital converters (ADC) it is extremely desirable to have an array of capacitors whose capacitances remain in a predetermined ratio to each other. However, the 16 bit or better accuracy now achievable with such ADC's require even more stable capacitance values over wide ranges of temperature. In typical integrated circuit fabrication the desired accuracy and stability is difficult to obtain because of parasitic capacitance which is inherently unstable and unpredictable and generally uncontrollable. A major source of parasitic capacitance in such capacitors occurs between the lower capacitor electrode on the substrate and the metal conductor which connects to the upper capacitor electrode. The dielectric medium of the parasitic capacitance is typically formed at least in part by the interlevel insulator which is a poor quality dielectric because its capacitance changes unpredictably upon application of an electric field. One commonly used such interlevel insulator which is desirable for a number of other reasons is borophosphate silica glass.